1. Field of the Invention
The present invention relates to a clock pulse transmission circuit which is suitable for use in carrying (transmitting and receiving) clock pulses having a constant duty factor between two units (apparatus or circuits) connected with each other by a transmission path such as, for example, a cable. More particularly, the present invention relates to a clock pulse transmission circuit which is capable of automatically correcting a change in the duty factor of the clock pulses, even if the duty factor is changed in the case where the clock pulses are transmitted between two units located apart from each other.
2. Description of the Related Art
Many of the semiconductor device testing apparatus (commonly called IC tester) for testing various types of semiconductor devices such as, for example, a semiconductor integrated circuit (IC) have a semiconductor device transporting and handling apparatus (hereinafter referred to as handler) connected thereto for transporting a semiconductor device to be tested or under test (commonly called DUT) to a testing or test section, followed by carrying the tested semiconductor device out of the test section and transporting it to a predetermined location. In a semiconductor device testing apparatus (hereinafter referred to as IC tester) of such type, a portion thereof called a test head which is disposed in the test section of the handler is formed separately from the IC tester proper, and the test head is connected to the IC tester proper by a signal transmission path such as, for example, a cable.
When clock pulses having a constant duty factor are transmitted as a pair of clock pulses comprising a clock signal having positive pulses (hereinafter referred to as positive clock pulses) and a clock signal having negative pulses (hereinafter referred to as negative clock pulses), there occurs a change in the duty factor between a transmitting circuit and a receiving circuit due to unbalances between sIgnal transmission length of the positive clock pulses and signal transmission length of the negative clock pulses as well as an amount of transmission loss of the positive clock pulses and an amount of transmission loss of the negative clock pulses, or due to differences in the transmitting and receiving circuits between a delay time caused when a clock pulse is changed from high level to low level and a delay time caused when a clock pulse is changed from low level to high level. Since this displacement of the duty factor sometimes becomes a cause for eventually degrading a timing accuracy of the IC tester, it is required to correct the displacement of the duty factor.
When clock pulses are transmitted at high speed with high accuracy between two units located apart from each other in an IC tester, there is generally used a differential transmission system wherein an emitter-coupled logic (hereinafter referred to as an ECL) is used. FIG. 8 shows an example of a conventional clock pulse transmission circuit of the differential transmission system using the ECL.
The clock pulse transmission circuit exemplarily shown comprises a transmitting unit (transmitting circuit) 1, a receiving unit (receiving circuit) 2, two transmission lines 9 and 10 for interconnecting those units 1 and 2. The transmitting unit 1 comprises a buffer 3 to which input pulses are supplied, a variable delay circuit 4 to which output pulses of the buffer 3 are supplied, a logic gate (OR gate) 5 to which output pulses of the variable delay circuit 4 and output pulses of the buffer 3 are supplied, and a driver 6 to which output pulses of the logic gate 5 are supplied.
The driver 6 comprises an ECL differential buffer and outputs a pair of positive clock pulses Sp and negative clock pulses Sn in response to the output pulses of the logic gate 5. Further, resistors 7 and 8 are serially inserted, respectively, into input terminals of the transmission lines 9 and 10 for transmitting the pair of clock pulses Sp and Sn outputted from the driver 6 to the receiving unit 2.
On the other hand, the receiving unit 2 includes a receiver 12 comprising an ECL differential buffer. Further, a termination resistor 11 is connected between termination terminals of the transmission lines 9 and 10.
In the conventional clock pulse transmission circuit constructed as described above, the displacement of the duty factor of the transmitted clock pulses is corrected such that the displacement of the duty factor of the clock pulses transmitted to the receiving unit 2 is detected by observing with an oscilloscope the positive and negative clock pulses (or either of the positive or negative clock pulses) outputted from the receiver 12 in the receiving unit 2, or by inputting the clock pulses to a comparator circuit to compare the clock pulses with reference clock pulses, and then the amount of delay of the variable delay circuit 4 in the transmitting unit 1 is adjusted in accordance with the magnitude of the detected displacement.
For example, it is assumed that when a set value of the varIable delay circuit 4 of the transmitting unit 1 is set to a middle value, and positive clock pulses having a 50% duty factor (refer to a waveform V2 in FIG. 9A) are generated through the logic gate 5 from positive clock pulses having a duty factor which is considerably smaller than 50% (refer to a waveform V1 in FIG. 9A), and then the positive clock pulses are inputted to the driver 6 to transmit positive and negative clock pulses Sp and Sn each having a 50% duty factor to the receiving unit 2 via the transmission lines 9 and 10, the duty factor of the positive clock pulses outputted from the receiver 12 in the receiving unit 2 has become smaller than 50% as shown in a waveformn V3 in FIG. 9A. In this case, the duty factor of the positive clock pulses outputted from the receiver 12 in the receiving unit 2 is adjusted to become 50% as shown in a waveform V3 in FIG. 9B such that the amount of delay of the variable delay circuit 4 in the transmitting unit 1 is set to large value to enlarge the pulse widths of the output pulses from the logic gate 5 as shown in a waveform V2 in FIG. 9B. Further, a waveform V1 in FIG. 9B is same as the waveform V1 in FIG. 9A.
However, in such an adjusting method, the displacement of the duty factor of the clock pulses received by the receiver 12 must be detected by observing with an oscilloscope the displacement of the duty factor or by inputting the clock pulses to a comparator circuit to compare the clock pulses with reference clock pulses, and thereafter the amount of delay of the variable delay circuit 4 in the transmitting unit 1 must be adjusted so that the detected displacement becomes zero. Therefore, there are problems that many operation steps are required in the adjustment work, and the adjustment work is complex and time consuming.
Moreover, due to an aged deterioration of the variable delay circuit 4 and other circuits in the transmitting unit, there is a problem that the amount of delay for setting the duty factor of the clock pulses (a set value of the variable delay circuit 4) is changed and the re-adjustment thereof is required.
It is needless to say that the above problems similarly occur not only in an IC tester but also in various instances for transmitting clock pulses between two units (apparatus or circuits) at high speed with high accuracy.